As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminated-based ball grid array (BGA) packaging and eventually to chip scale packaging.
Any advancement in IC chip packaging technology is driven by ever-increasing needs for achieving better performance, greater miniaturization and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
One specific form of chip scale package (CSP) is wafer level package (WLP). WLP adopts an area-array packaging approach that is utilised in BGA packaging. This approach enables WLP to have a packaging outline that is substantially identical in size to the IC chip, making WLP the smallest form of CSP. WLP allows the IC packaging process to be carried out at wafer level as well as incorporate wafer level reliability and facilitate IC burn-in test.
Efforts have been expended by many to propose a low-cost IC packaging solution in order to meet the ever-increasing demand for better wafer-level performance.
Wafer level packaging has therefore attracted immense interest in the electronics industry for being a potential solution in IC packaging process that can provide low-cost production through large-scale manufacturing.
U.S. Pat. No. 6,605,525 to Lu et al. proposes a thick stress buffer layer to be used between chip pad metallisation and redistribution layer. Solder bumping is carried out over the thick stress buffer layer to achieve WLP.
In “The Ultra CSP (tm) Wafer Scale Package”, High Density Interconnect Conference and Expo, Tempe, AZ, Sep. 15–16, 1998 published by Peter Elenius and Hong Yang, a fabrication method for forming WLP by using solder bumps is disclosed. The solder bumps are supported by polymer collars and are soldered on a polymer substrate.
In a commercial literature titled “Super CSP” published by Fujitsu Microelectronics America, Inc, copper posts are shown to be used as a form of interconnection for connecting the solder bumps to the redistribution layer.
U.S. patent application Ser. No. 2003/0122229-A1 by Bakir et al. proposes a fabrication method for fabricating ultra fine-pitch WLP through the use of specialized proprietary materials to achieve fine-pitch compliant interconnects.
While the foregoing prior art disclose various methods for fabricating WLP, these methods have inherent limitations in relation to the use of common fabrication materials to achieve high frequency performance. Undesirable parasitic capacitance and inductance are typically present in WLP fabricated by conventional methods that use common fabrication materials. This renders unsuitable the use of these methods for fabricating WLP used in high frequency domains of RF and microwave applications. In prior art proposing the use of specialised proprietary materials, this results in the lowering of cost efficiency of fabricating WLP.
Accordingly there is a need for a method for WLP fabrication for achieving high frequency performance using common IC fabrication process and materials for large-scale industrial applications.